Data processing machines typically include numerous data paths across which data are transmitted between sections of the machine. The data transmitted between sections of the machine. The data transmitted across the data paths are often partitioned into groups of bits, such as words containing 16 bits each, bytes containing 8 bits each, or digits containing 4 bits each.
In order to detect errors occurring within the groups of bits, a parity bit or other error code is associated with individual groups of bits being transmitted on the data path.
Thus, a data path will transmit a field of bits of data which are partitioned into groups. Associated with each group in the field, a parity bit is also supplied across the data path.
The data paths are enabled in response to a control signal. Typically, each individual line is enabled by an enabling gate which receives a copy of the control signal. Because of the large number of enabling gates required for some data paths, multiple copies of the control signal are fanned out by control signal power gates.
Prior art systems have been unable to detect errors occurring in these control signal power gates. Thus, it is possible for an error in a control signal power gate to go undetected in the machine, leading to unacceptable machine performance.
FIG. 1 illustrates a prior art system for enabling a data path.
The data path includes a field 11 of bits B0:B2, P which include a group of bits B0-B2 and a parity bit associated with the group. Only one group of bits is shown in the embodiment of FIG. 1 in order to simplify the description. It should be appreciated that multiple groups of bits with associated parity bits could be implemented. The field 11 of bits in the data path are supplied individually to data path enabling gates 12. Thus, bit zero B0 is supplied as one input to gate 13, bit one B1 is supplied as one input to gate 14, bit two B2 is supplied as one input to gate 15 and the parity bit P is supplied as one input to gate 16. The second input of the enabling gates 12 is a copy of the control signal CTL. The control signal CTL is supplied on line 17 to power gate 18 for copy zero C0 and power gate 19 for copy one C1 of the control signal. Power gates 18 and 19 supply an inverted version of the control signal on lines 20 and 21, respectively. Line 20 supplies one input to gate 13 and one input to gate 14. Line 21 supplies one input to gate 15 and one input to gate 16. Thus each power gate supplies a respective copy C0, C1 of the control signal CTL to two enabling gates within the field 11.
The inputs to the enabling gates are inverted, as indicated by small circles in the figure, in order to account for the inverting effect of the power gates 18 and 19.
When the control signal CTL is asserted, the enabling gates 12 supply the field 11 including bits B0-B2 and the parity bit P to the data path 22. A parity checker 23 receives the parity bit P from gate 16, and bits B0-B2 from gates 13-15. If the parity check detects an error, then an error signal is supplied on line 24.
The embodiment shown in FIG. 1, however, is unable to detect in all cases a failure in one of the control signal copies from power gates 18 or 19. In this particular embodiment, a 25% probability of not detecting a damaging failure in one of the control line copies exists. If one of the power gates 18, 19 fails, then there is a 25% probability that the outputs of the respective enabling gates will produce a benign failure and a 50% probability that they will produce a detectable error. For instance, if the output of power gate 18 is erroneously asserted, then enabling gates 13 and 14 will supply bits B0 and B1 in the form supplied at the input field 11. Since the output of the power gate 18 should not be asserted, the outputs of the gates 13 and 14 should be both zero. For example, in an even parity machine there is a 25% chance of a benign failure because one of the four possible states of bits B0 and B1 is the desired value of 00. Two of the possible states of bits B0 and B1 are 01 and 10. If these values are supplied on the data path 22, then the parity checker 23 will detect an error because of the single bit deviation from the preferred value of 00. Thus, there is a 50% chance of a detected error. However, if bits B0 and B1 supply values 11 to the data path 22, then the parity checker 23 will not detect the error. Therefore, a 25% chance exists of an actual damaging error occurring that goes undetected by the parity checker 23 due to the failure of the power gate 18.
Thus, as can be seen in FIG. 1, there always exists a probability that an error occurring in a power gate 18, 19 will go undetected. The following discussion provides a generalized description of the probability of detecting a failure in a control line copy using data path parity checkers, such as the parity checker 23 shown in FIG. 1.
If a control line copy affects n bits of an m bit wide parity checked field (where m includes both the data and parity bits), the following can be stated about the probability of detecting a failure in the control line copy:
(a) If n=m PA0 (b) If n.noteq.m,
(i) Erroneously Asserted Output of Power Gate
For this case, the affected enabling gates should produce all 0's but instead transfer to their outputs the values of their inputs. PA1 One failure mode is benign (b) when the actual outputs are all 0's. All other failure modes go undetected since the data and parity at the inputs of the affected enabling gates are passed unaltered to the outputs. PA1 For this case, the affected enabling gates should transfer to their outputs the values of their inputs but instead produce all 0's. PA1 One failure mode is benign (b) when the should be outputs are all 0's. All other failure modes go undetected since the affected enabling gates generate all 0's (i.e. 0 data with good parity). PA1 p(b)=2 in 2 * 2.sup.m =2.sup.(-m) PA1 p(d)=0 in 2 * 2.sup.m =0 PA1 p(u)=1-(p(b)+p(u))=1-2.sup.(-m) PA1 For this case, the affected enabling gates should produce all 0's but instead transfer to their outputs the values of their inputs. PA1 (1) Half of the failure modes are detected failures since half of the possible 2.sup.n actual output values from the affected enabling gates produce parity errors when combined with the all 0's outputs of the m-n unaffected enabling gates. This statement is based on the fact that for an n bit number, 2.sup.(n-1) of the possible values have even parity and 2.sup.(n-1) have odd parity. When combined with the even parity of the unaffected enabling gate output values, the affected enabling gate actual output values which have odd parity produce parity errors. Likewise, the affected actual output values which have even parity produce no parity errors. PA1 (2) Of the remaining 2.sup.(n-1) failure modes which are undetected failures, 1 mode is benign when the actual output values of the affected enabling gates are all 0's. All other modes are undetected, damaging failures. PA1 For this case, the affected enabling gates should transfer to their outputs the values of their inputs but instead produce all 0's. PA1 (1) Half of the failure modes are detected failures since half of the possible 2.sup.n should be output values from the affected enabling gates have parities opposite the all 0's parity actually produced by the enabling gates. This statement is based on the fact that for an n bit number, 2.sup.(n-1) of the possible values have even parity and 2.sup.(n-1) have odd parity. When the all 0's, even parity of the affected enabling gate actual output values is combined with the parity of the unaffected enabling gates output values, the affected should be output values which have odd parity result in parity errors. Likewise, the affected should be output values which have even parity result in no parity errors. PA1 (2) Of the remaining 2.sup.(n-1) failure modes which are undetected failures, 1 mode is benign when the should be output values of the affected enabling gates are all 0's. All other modes are undetected, damaging failures. PA1 p(b)=2 in 2 * 2.sup.n =2.sup.(-n) PA1 p(d)=2 * 2.sup.(n-1) in 2 * 2.sup.n =0.5 PA1 p(u)=1-(p(b)+p(u)=0.5-2.sup.(-n)
(ii) Erronously Not Asserted Output of Power Gate
(iii) Probabilities
(i) Erroneously Asserted Output of Power Gate
(ii) Erroneously Not Asserted Output of Power Gate
(iii) Probabilities
As can be seen from the foregoing discussion, as a power gate affects an increasing number of bits in a single parity checked field, the probability of an undetected, damaging failure increases due to the occurrence of an error in a power gate. Thus, there is a need for a mechanism that will reduce the probability of an undetected damaging error due to a failure in a power gate.